IBIS Macromodel Task Group

Meeting date: 14 October 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
* Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Joe Abler, IBM
  John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
  Michael Mirmak, Intel Corp.
* Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
* Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
* Pavani Jella, TI
  Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
  Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems


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Opens:

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Call for patent disclosure:

- No one declared a patent.


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Review of ARs:

- Todd check on permission for Mike L to post Interconnect SPICE syntax
  - Done
  - We will wait to hear from Synopsys legal

- Fangyi prepare presentation on high order C modeling
  - Done

- Arpad try to find material on series-parallel RC models
  Done

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
          - [External ...] also?
          - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - Deferred until a demand arises or we have nothing else to do

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New Discussion:

Arpad showed his June 2004 IBIS summit presentation:
- "I-V curve linearity and buffer impedance"
- Slide 5:
  - Zac is the tangent line
  - Zdc is the end-to-end slope
  - Zac and Zdc differ
- Slide 10:
  - At low frequency the curve matches slide 5
  - The curve does not look right at higher frequencies.
  - This is expained by Miller capacitance coupling the pre-driver
- Slide 12:
  - Adding Miller capacitance improves accuracy

Arpad showed his June 2001 IBIS summit presentation:
- "High Accuracy Behavioral Modeling for Frequency and Time Domain Simulations"
- Transfer functions can be modeled with G elements
- A simple RCG circuit can model voltage dependence
- The frequency domain response is good
- David: Was this ever proposed for IBIS?
  - Arpad: It would have involved complex number capability
- The RC ladder circuit is not magic, it just happens to model closely

Fangyi showed his document:
- "Modeling Nonlinearity in Response Function"
- Time-independent equation can be generalized to be time dependent
- A derivative expansion method is used
- Two nonlinear no-memory functions can be combined
- With memory functions a Wiener series can be used
- The memory function is used to model voltage dependency
- We need to measure frequency response using a time varying V source
- Arpad: Would time domain simulation be used to generate this data?
  - Fangyi: Two frequency sweeps are needed:
    - input sweep
    - bias sweep
- Bob: Is output measured as amplitude and phase?
  - Yes
- Arpad: So the simulator would implement the equations, and the model
  would have only coefficients?
  - Yes
- Fangyi: The Weiner representation is the important part
- Arpad: Nonlinearity captures the shape of the I-V curve
- Arpad: What happens when the buffer switches from one I-V to the other?

Arpad: How does this compare to Michael M proposal?

Walter showed slide 11 from Arpad's June 2004 presentation:
- This doesn't show the C_comp that is usually present
- Walter showed a slide "Isolate IBIS IV from Final Stage"
- Michael M circuit shows an RC final stage
  - May have some voltage dependence
- Final stage at high speeds can look like a low pass filter
- At 3GHz+ we are seeing this
- The proposals we have seen are ways of modeling this final stage
  - The final stage can be a box
  - Arpad: It depends on how radically we want to move away from IBIS today
    - This may run out of steam eventually
    - Would prefer to have control over actual buffer impedance
  - Walter: Current IBIS not sufficient above 5GHz
    - Elements beyond RC needed to model final stage
    - Can be implemented in HSPICE or IBIS Interconnect SPICE
    - We have heard 4 solutions so far
      - A final stage box can implement all
  - Arpad: The best match would be the model itself
    - Walter: This would be the best behavioral approach
- Walter: The final stage subckt would have stimulus, enable, and power nodes

AR: Walter prepare presentation on final stage proposal

AR: Arpad send Fangyi Rao presentation to Mike L for posting

Next meeting: 14 October 2008 12:00pm PT

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